1. Field of the Invention
The present invention relates to power amplifier control circuits, and in particular, to power ramp up and ramp down control circuits for power amplifiers.
2. Description of the Related Art
Power amplifiers for amplifying radio frequency (RF) signals for wireless transmission are used in many applications. One increasingly common application is that of a radio telephone communication system, such as a cellular telephone system. One example of such a system is a time division multiple access (TDMA) communication system, such as that based upon the Global System for Mobile Communication (GSM) standard. In such a system, relatively narrow single channels within the prescribed RF spectrum are shared by multiple telephones, with each one being allocated a specific time slot on a repetitive basis. During its assigned time slot, the transceiver must set its outgoing signal to the appropriate frequency and ramp up the power level of such signal by ramping up the power amplification of the power amplifier to the appropriate level. Once the data has been transmitted, the power amplification of the power amplifier must then be ramped down prior to the beginning of the next time slot so as to not cause interference with the user assigned to that time slot.
This ramping up and down of the power amplification provided by the power amplifier defines a power profile which must be maintained in accordance with strict specifications. If such power ramping is not accurately controlled then spurious and other undesired signals may be generated in adjacent time slots or at improper frequencies, thereby causing interference with other users within the system, as well as possibly causing interference with other users of other systems elsewhere within the RF spectrum.
The conventional technique to maintain this control over the power amplifier uses a feedback loop with a reference power ramp curve that is generated in accordance with a programmable power profile data table which drives a digital-to-analog converter (DAC). Generally the ramp generator circuit is implemented in an integrated circuit (IC) and the power control loop itself is implemented using components external to such IC. (Examples of this approach can be found in the disclosures of U.S. Pat. Nos. 5,150,075 and 5,748,037, the disclosures of which are incorporated herein by reference.) Typically some form of processor, such as a microprocessor or digital signal processor, is used to generate the ramp and exercise control over the feedback loop for the power ramp control circuit.
While such systems perform reasonably well, they nonetheless suffer from a number of disadvantages. For example, due to the use of external components for the power control loop itself, it is difficult, if not impossible, to control the dynamic range of the loop. Plus, the use of external components is generally significantly more expensive than if the power control loop were more fully integrated with the ramp generator circuit. Furthermore, any control over the power control loop itself would require additional control tasks to be performed by the microprocessor or DSP. Accordingly, it would be desirable to have a power amplifier control loop which can be subjected to greater levels of control without requiring additional processor resources.